Learn VHDL A Course by Pro.Tips
A fun way to learn VHDL by designing projects

Course goals
• Students will gain ability to design synthesizable circuits that can be translated into hardware such gates, registers and RAM’s.
• Students will gain ability to design testbenches that verify the functionality of the HDL (Hardware Description Language) design by checking the output matches its specifications.
• Students will learn to use Mentor Graphics ModelSim software along with Lattice Diamond to design HDL code, simulation and verification, and synthesis of HDL code into logical gates
• Students will learn to HDL designs optimization techniques for fitting on chip.
• Students will see examples of synthesizable VHDL code throughout the course and demonstrated their designs successfully loading on Lattice MachXO3 Device

Required software’s
• Lattice Diamond along with ModelSim
• No hardware required
• However, examples will be shown successfully loading on MachXO3 development board device

Course sections
• Introduction – Include course overview and software install instructions for software Lattice Diamond along ModelSim which will be used throughout the course.
• Basics of VHDL – Discuss various features of the language via examples, including Entity, Architecture, Library and Use Clauses, Data Types, Signals, Variables, Processes, Concurrent Statements, Sequential Statements, Conditional Statements, Loops, Component Instantiation, Packages, State machines, Testbenches etc
• Projects – Design 3 projects using VHDL
• Bonus material

Github files – https://github.com/protipswebsite/learn-vhdl